FIG. 7 illustrates a circuit example of a step-down switching regulator of a current mode control type. Referring to FIG. 7, a switching regulator 100 steps down an input voltage input to an input terminal IN to be a predetermined voltage and outputs the stepped down voltage as an output voltage Vo from an output terminal OUT.
FIG. 8 is a timing chart illustrating an example of operation of the switching regulator 100 illustrated in FIG. 7. Referring to FIG. 8, a referential mark Io designates an output current output from an output terminal OUT; a referential mark Ve designates an error voltage, which is an output voltage of an error amplifying circuit 120; a referential mark Vslp designates a slope voltage, which is an output voltage of a slope voltage generating circuit 110; a referential mark Set designates a set pulse signal, which is an output signal of an oscillating circuit 140, input to a set input terminal S of an RS flip-flop circuit 150; a referential mark Rst designates a reset pulse signal, which is an output signal of a PWM comparator 130, input to a reset input terminal R of the RS flip-flop circuit 150; and a referential mark S1 designates a gate signal of a switching transistor M101, which is a signal obtained by inverting an output signal output from an output terminal Q of the RS flip-flop circuit 150 using an inverter circuit 160.
Referring to FIG. 8, the set pulse signal Set is output from the oscillating circuit 140, which becomes a high level at predetermined time intervals. When the set pulse signal Set is input to the set input terminal S of the RS flip-flop circuit 150, the output terminal Q of the RS flip-flop circuit 150 outputs a signal of high level. Because the signal level of the signal is inverted by the inverter circuit 160, the gate signal S1 of the switching transistor M101 becomes a low level. Then, the switching transistor M101 is switched on and an input voltage Vi is input to a series circuit of an inductor L101 and an output capacitor C101.
An inductor current IL flowing through the inductor L101 linearly increases as time advances. When the inductor current IL increases to be more than the output current Io, electric charges are accumulated in the output capacitor C101, and the output voltage Vo increases. The slope voltage generating circuit 110 detects the inductor current IL, converts the inductor current IL to a voltage, and simultaneously generates a compensating voltage for avoiding a sub-harmonic oscillation. The slope voltage generating circuit 110 adds the compensating voltage to the voltage obtained by converting the inductor current IL to generate the slope voltage Vslp and outputs the slope voltage Vslp to the PWM comparator 130. The slope voltage Vslp linearly increases while the switching transistor M101 is switched on.
The error amplifying circuit 120 amplifies a difference voltage between an output voltage detecting signal Vfb and a reference voltage Vref and outputs the amplified voltage as an error voltage Ve. The PWM comparator 130 compares the error voltage Ve with the slope voltage Vslp, and outputs the signal Rst of high level when the slope voltage Vslp exceeds the error voltage Ve to reset the RS flip-flop circuit 150. Then, the output terminal Q of the RS flip-flop circuit 150 returns to the low level, and the gate signal S1 becomes the high level. Therefore, the switching transistor M101 is switched off.
When the switching transistor M101 is switched off, a voltage VLX of a connection node LX decreases to a minus voltage due to a function of a back electromotive force generated by the inductor L101. Then, a rectifying diode D101 is switched on to make energy accumulated in the inductor L101 flows out. Therefore, the inductor current IL linearly decreases as time advances. When the inductor current becomes smaller than the output current Io, electric power is supplied from the output capacitor C101 to a load 200 to thereby decrease the output voltage Vo. After a cycle, the set pulse signal Set is generated from the oscillating circuit 140 to switch the switching transistor M101 on again. Then, the inductor current IL is supplied to increase the output voltage Vo. Subsequently, similar operations are repeated.
Referring to FIG. 8, the output current Io is low before a time t2. The output current Io is decreased here. The output voltage Vo slightly increases as time advances while the output current Io is decreased. Therefore, the error voltage Ve further decreases and becomes a lower limit value of the slope voltage Vslp or less at the time t1. Then, the output signal Rst of the PWM comparator 130 becomes the high level to reset the RS flip-flop circuit 150. In this situation, since the signal level of the output terminal Q does not invert even though the set pulse Set is input to the set terminal S, the switching transistor M101 is not switched on.
When the output current Io rapidly increases at the time t2, the output voltage Vo decreases as illustrated in FIG. 8. However, the error voltage Ve of the error amplifying circuit 120 does not increase as much. This is because electric charges in a phase compensating capacitor Ch are discharged to be zero volts (0 V) while the error voltage Ve of the error amplifying circuit 120 is zero volts (0 V), and therefore the error voltage Ve does not rise until the capacitor Ch is charged to a predetermined voltage. For the reason, the gate signal S1, which switches on the switching transistor M101 upon a change of the output signal Rst to be the low level caused by an excess of the error voltage Ve over the lower limit value of the slope voltage Vslp, is first output at a time t3 after a time t2, when the output current Io rapidly increases, by a time period Td. Between the time t2 and the time t3, the output voltage substantially decreases.
In the related art described in, for example, Japanese Unexamined Patent Application Publication 2006-94572, a switch is provided to hold, or charge or discharge electric charges in a phase compensating capacitor included in a feed-back circuit of an error amplifying circuit. By operating the switch, a stabilization time for an error voltage output to a voltage comparator is shortened. In this way, an output voltage output to a load can be smoothly changed to a predetermined set voltage.
However, the technique described in the related art has problems such that the switch and a control circuit for controlling the switch are additionally necessary and an entire circuit becomes a large size. Further, it is possible to convert an input voltage to an output voltage and output the output voltage from an output terminal of a device determined by arbitrarily choosing a switching regulator or, under a light load, a second DC-DC converter having a power conversion efficiency higher than that of the switching regulator, or by choosing one of the switching regulator and the second DC-DC converter when a predetermined condition where a load current increases and decreases around a predetermined current, for example. However, when the second DC-DC converter is switched to be the switching regulator, there is a problem such that the output voltage Vo substantially decreases for the above reason.